The present invention relates generally to methods and apparatus for conducting failure analysis in integrated circuits. More specifically, the invention relates to methods and apparatus for using Optical Beam Induced Current to analyze failure modes discovered with a functional tester.
Integrated circuits ("ICs") must be subjected to failure analysis during development, manufacturing, and after failure in the field. In failure analysis, an IC is subjected to various electronic tests to determine whether an expected electronic result is obtained for each test. This may involve applying a defined set of inputs to input pads of a test IC and monitoring the signals at output pads of the IC. If the monitored set of signals at the output pads does not match an expected set of values, then the IC has in some way failed.
To perform a detailed analysis of an IC's circuitry, a set of "vectors" may be provided to the IC input pads. Each vector is a time varying sequence of input values provided to the input pads of the test IC. By providing a time varying set of input values (a vector), the internal circuitry of the IC may be probed. And by providing a series of such vectors, various possible failure modes throughout the IC may be investigated.
Testing an IC with a set of vectors is commonly referred to as "functional testing" and the apparatus employed to perform functional testing is called a "production tester" or a "functional tester". Such production testers include at least a clock, a series of input connectors for connecting to the IC input pads, a series of output connectors for connecting to the IC output pads, Vdd and Vss inputs, and a controller for generating the vector signals applied to the input pads. To provide thorough testing of an IC, the production tester should have as many input and output connectors as input and output pads on the IC. Thus in 1996 technology, it is not uncommon for a production tester to have more than 500 input and output connectors.
While production testers can determine which vectors elicit failures in an IC, often they can not pin-point the source of the failure within the IC circuitry. They simply identify that a dynamic set of electronic inputs has, at some cycle, exhibited an unintended output. That unintended output may be the result of a short between two devices, a faulty connection to a device, a failed device, etc. The exact device or circuit causing the failure and the structural nature of the failure can not be ascertained with production tester alone. Therefore, IC developers and manufacturers have deployed various probe techniques for pin-pointing IC structures causing failures.
Electron beam probes have been used to generate SEM-like images of an IC. While these images can locate gross structural defects in an IC, they can not easily determine whether current flows between two elements of an IC circuit. Further, electron beam probing must be performed in a vacuum system. Thus, the experimental apparatus and protocol is quite expensive.
Emission microscopy has been employed to image current flow in an operating IC. Emission microscopy employs a radiation detector to identify locations on an IC where radiation is emitted as a result of flowing current. This technique relies on the physical principle that current flowing within an IC will emit some small amount of radiation and that the origin of that radiation can be resolved by microscopy. While this technique can determine the locus of some IC defects by identifying current paths, it is relatively insensitive; only very low intensity radiation is generated by the very low currents flowing in an IC powered by Vdd. Typically, emission microscopy can detect currents no smaller than nanoampere range currents. Further, the technique relies upon currents induced by tester signals provided to signal input pads of an IC in conjunction with the power provided to the cell during normal operation. Thus, it may be difficult to identify latent defects which will manifest themselves only after substantial use.
Optical Beam Induced Current ("OBIC") techniques also locate current flow in an IC, but are more sensitive than emission microscopy techniques. Further, since the physical principles underlying OBIC and emission microscopy are different, OBIC can be used to find different failure modes than those located by emission microscopy. An OBIC is induced upon application of a light beam to a p-n junction in a semiconductor device. The induced current may be collected through Vdd pins. When a current is detected, it is known that the current has been induced at the location where the light beam is currently focused. The OBIC technique is described in various sources. See for example, H. Komoda et al., "Detection of Open Contact Using Optical-Beam-Induced Current Techniques" Jpn. J. Appl. Phys., Vol. 33, pp. L1070-L1072 (1994). Briefly, the technique works as follows. When an optical beam is projected onto a depletion layer (as near a p-n junction), a conduction electron-hole pair is generated in the depletion layer. If the electric field in the depletion region is sufficiently great, the electron and hole will drift in opposite directions without recombining. Thus, the electron and hole will flow out of the junction resulting in an OBIC signal.
OBIC techniques have been employed with static testers to detect IC defects. Such testers employ a power supply such as constant current source and may rely upon a single set of inputs to a small group of IC pads (provided by, for example, a switch box). They have no clock or other functionality for generating a dynamic series of inputs. Thus, they can not generate one or more complicated vectors such as are produced by a production tester. While static testers can, in conjunction with OBIC techniques, locate some IC defects (usually by chance in a complicated IC), they are limited to simple failure modes such as those that might appear in peripheral circuits of an IC (e.g., I/O slot circuits). OBIC testers employing a constant current source are described in U.S. Pat. No. 5,430,305 issued to Cole Jr. et al. and in a related article by Cole Jr. et al., "Novel Failure Analysis Techniques Using Photon Probing With a Scanning Optical Microscope" IEEE/IRPS, pp. 388-398 (1994).
U.S. Pat. No. 5,453,994 issued to Kawamoto et al. describes an OBIC test system in which an IC is subjected to a series of inputs from a clock controlled tester. At each clock cycle, the IC output pads are monitored for an expected result. Also at each cycle, an optical beam from an OBIC test apparatus is directed to a specific drain location on the IC. The locations the optical beam are chosen to test specific drain regions at specific cycles. If the signals on the output pads depart from the expected values at any cycle, it is assumed that the drain currently subjected to optical probing has a defect.
While the technique described in U.S. Pat. No. 5,453,994 probes individual devices with the sensitive OBIC technique, it is limited to testing know devices at specified cycles. If a vector introduces a failure at some location other than the device currently being probed, the locus of the failure is unknown. Further, the technique requires specially designed tester. The operation of the tester has to be sequencialized with the OBIC beam. Thus, the tester will be more complicated and more expensive than an existing production tester. In fact, no currently available tester type can be used with this method.
As yet, there is no technique for forcing an IC into a failing state--as with a production tester--and performing OBIC to determine a failing site. This is due at least in part to the problem of obtaining an OBIC signal when a test IC is coupled to a production tester. Specifically, if a tester is connected to the IC, the tester will short the OBIC signal coming from the device's Vdd pin(s) by shunting the signal to ground (Vss) when the Vdd and Vss contacts are connected to a power supply as it is in a production tester.
Thus, there is a need for an OBIC detection system that can take advantage of a sophisticated testing procedure which will force a test IC to show its failure state.